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Static Switch Description

Abstract

The switch is configured to transfer on three modes of abnormal operation:

1. The Failure Or Deterioration Of The Inverter Square Wave. Practically all possibilities of inverter component failures result in the deterioration or complete collapse of the square wave. This is the earliest sign that the inverter output (out of the CVT) will be sustained for only a few more milliseconds. The electrical "momentum" of the CVT causes the output to be sustained for a few milliseconds following a failure at the input.

2. The Failure Or Deterioration Of The Sinusoidal Output Voltage Of The Ferroresonant Filter 1cvt1. The reason for sensing at this point is to spot a failed CVT, even though it is an extremely longlife device. A break may occur, but it will be no more than %-cycle.

3. A Branch Load Fault Or Simply An Overload Which Exceeds The Current Capacity Of The Inverter And Cvt. This mode is useful for clearing branch fuses in the shortest possible time (the actual clearing time is more dependent on the auxiliary source and the fuse characteristics than on the static switch). This mode is also useful for preventing an inverter overload, which collapses output voltage, when load for any reason accumulates beyond the inverter rating, whether by accident or intent.

Item 1 and associated logic and power circuitry constitutes the basic static switch. Items 2 and 3 constitute accessory functions which provide two more inputs to the failure logic. Item 3, for instance, may have no meaning or utility if only a single steady load is connected to the inverter. In this case, the static switch is used only for detecting and transferring upon inverter failure.

The design of the logic and power sections of the switch represent an attempt to use the least possible number of components to cover almo all possibilities of failure - no circuit is perfect.

Refer to circuit diagram:

The square wave sensing (Item 1) is accomplished by stepping down the square wave voltage from 130 volts peak to about 18 volts peak and rectlying (T, and IB, integrated bridge rectifier). The resultant DC is as shown on the diagram. The spikes which fail to the axis are due to the finite rise time of the original square wave. If the spikes ever increase in width 2E the DC falls to zero, a transfer should occur. In other words, a decent rectified square wave should never spend more than a few microseconds at any voltage other than the peak value. Notice that the state of the reed relay (RR) determines which set of parallel power SCRs are conducting; i.e., when RR is energized, SCRs 5 and 6 are supplying load current, and when RR is de-energized, SCRs 3 and 4 supply load current. Notice also, that the conduction state of SCR-1 determines the position of the reed relay. In normal operation, SCR-1 is conducting, having been Malty gated gn by the operator depressing the retransfer pushbution (PB-1) at start-up. Once conducting, SCR-2 remains pj2 unfil current through it drops at start-up. Once conducting, SCR-2 remains gn until current through it drops below the "holding" value. "Holding" current of an SCR Is roughly one-thousandth of the full load rating. Capacitor C,, however, is not capable of supporting the holding current for longer than a few microseconds; therefore, when a failure occurs or square wave rise time increases (a symptom of impending failure), the SCR ceases to conduct, and the reed relay de-energizes. The reed relay operates in 50 microseconds to close the gates of the auxiliary source SCRs 3 and 4, and open the gates of the CVT SCRs 5 and 6. Because of the nature of SCRs to remain conducting until the current through anode-cathode goes to approximately zero, this Is a no-break transfer with as much as 81A milliseconds (halfcycle at 60 Hz.) of overlap where the CVT mW the auxillary source supply load power. Because of the "carry over" effect of the CVT, the output of the CVT has not had time to deteriorate prior to the line SCRs being gated 2n.

The CVT current limiting characteristic and the CVT - auxiliary source phase coincidence reduce circulating currents during the period of parallel operation. The retransfer is initiated by pressing PB-1 and reversing the previous events.

It should be point out that a phase-lock synchronizing circuit is used to synchronize the inverter output to the auxiliary source when a static switch is to be employed. This minimizes the load voltage disturbance during the transfer and retransfer operation. Also, for manual transfer and retransfer operations, the static switch is inhibited by the sync circuit until an in-phase sync is achieved. In the automatic mode of transfer (failure transfer), no inhibits are allowed, since a lack of transfer may be worse than an out-of-sync transfer.

Fail safe logic has been employed where possible to cause a normal transfer to the auxiliary source when any part of the logic board fails to function. Almost any logic component failure causes the reed relay to de-energize and thereby engage the auxiliary source. A reed relay coil failure also causes a normal transfer.

Operating Mode Number 3 goad current sensing) is indicated in the doffed portion of circuit. A current transformer (CT1) senses output load current and causes the voltage across Rto vary as the output current varies. R, is setto develop a voltage which fires SCR-2 when load current exceeds the peak value of normal load current. SCR-2 causes the reed relay to de-energize, and transfer occurs to auxiliary source as before. When the load is decreased to normal limits, a manual retransfer can be initiated by pressing pushbuffon PB-1.

Operating Mode Number 2 consists of a low voltage sensing circuit which forces a transfer if the output voltage fails or drops below a predetermined value. This circuit is basically a uninjunction timer, which is reset by normal sine wave output. If the sine wave deteriorates or fails altogether, the timer will time out and fire SCIR-2. this will cause a transfer in the same way as R does with an overcurrent (disi-!jssed above). Transfer time will depend on how long it takes the timer to "time-out." this value is normally set to less than four milliseconds.

In addition to the redundancy advantages of using the static switch, is the incidental advantage of being able to start loads having an in-rush current much greater than the current limit point of the inverter. Once started, the inverter can perform a no-break take-over of the load by initiating the manual retransfer.

For reasons of clarity, the indicating lights, fuses and circuit breakers are not shown on the drawing. In general, the value of fuses, circuit breakers, power SCRs, and associated components, are far large r than required to meet the rated conditions.

100% Non-Linear Or Crest Factor Proven Circuit

Included in this equipment is circuitry to allow SCI's inverter to be compatible with loads exhibiting a high crest factor. Today's electronic computers and instrumentation equipment are powered with high frequency switching power supplies, which draw non-linear current from the AC source.

SCI's UPS incorporates a constant voltage transformer in their inverter design that has unique energy storage properties, which enable SCI inverters to provide the high peak current required by todays computers and instrumentation.

Together with SCI's "zero-break" static switch with its unique logic circuit that differentiates between true overcurrent conditions and non-linear/crest factor loads, SCI alone offers a truly coordinated system to power your load.